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FEATURES 5 V Stereo Audio DAC System Accepts 16-/18-/20-/24-Bit Data Supports 24 Bits and 96 kHz Sample Rate Multibit Sigma-Delta Modulator with "Perfect Differential Linearity Restoration" for Reduced Idle Tones and Noise Floor Data Directed Scrambling DAC--Least Sensitive to Jitter Differential Output for Optimum Performance 113 dB Dynamic Range at 48 kHz Sample Rate (AD1854KRS) 112 dB Signal-to-Noise at 48 kHz Sample Rate (AD1854KRS) -101 THD+N (AD1854KRS) On-Chip Volume Control with 1024 Steps Hardware and Software Controllable Clickless Mute Zero Input Flag Outputs for Left and Right Channels Digital De-Emphasis Processing Supports 256 F S or 384 F S Master Mode Clock Switchable Clock Doubler Power-Down Mode Plus Soft Power-Down Mode Flexible Serial Data Port with Right-Justified, LeftJustified, and I2S-Compatible 28-Lead SSOP Plastic Package APPLICATIONS DVD, CD, Set-Top Boxes, Home Theater Systems, Automotive Audio Systems, Sampling Musical Keyboards, Digital Mixing Consoles, Digital Audio Effects Processors
Stereo, 96 kHz, Multibit DAC AD1854
PRODUCT OVERVIEW
The AD1854 is a high performance, single-chip stereo, audio DAC delivering 113 dB Dynamic Range and 112 dB SNR (A-weighted--not muted) at 48 kHz sample rate. It is comprised of a multibit sigma-delta modulator with dither, continuous time analog filters and analog output drive circuitry. Other features include an on-chip stereo attenuator and mute, programmed through an SPI-compatible serial control port. The AD1854 is fully compatible with current DVD formats, including 96 kHz sample frequency and 24 bits. It is also backwards compatible by supporting 50 s/15 s digital de-emphasis intended for "redbook" 44.1 kHz sample frequency playback from compact discs. The AD1854 has a very simple but very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers and sample rate converters. The AD1854 can be configured in left-justified, I2S, and rightjustified. The AD1854 accepts serial audio data in MSB first, twos-complement format. A power-down mode is offered to minimize power consumption when the device is inactive. The AD1854 operates from a single 5 V power supply. It is fabricated on a single monolithic integrated circuit and housed in a 28-lead SSOP package for operation over the temperature range 0C to 70C.
FUNCTIONAL BLOCK DIAGRAM
CONTROL DATA INPUT 3 DIGITAL CLOCK 96/48FS SUPPLY IN CLOCK 2
VOLUME MUTE
AD1854
8 FS INTERPOLATOR 8 FS INTERPOLATOR
SERIAL CONTROL INTERFACE
VOLTAGE REFERENCE
CLOCK CIRCUIT
16-/18-/20-/24-BIT DIGITAL DATA INPUT SERIAL 2 MODE
SERIAL DATA INTERFACE
ATTEN/ MUTE ATTEN/ MUTE
MULTIBIT SIGMADELTA MODULATOR MULTIBIT SIGMADELTA MODULATOR
DAC
OUTPUT BUFFER OUTPUT BUFFER ANALOG OUTPUTS
DAC
2 PD/RST MUTE DE-EMPHASIS ANALOG SUPPLY
2 ZERO FLAG
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD1854-SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD) Ambient Temperature Input Clock Input Signal Input Sample Rate Measurement Bandwidth Word Width Load Capacitance Load Impedance Input Voltage HI Input Voltage LO
5.0 V 25C 12.288 MHz (256 x FS Mode) 1.0013 kHz -0.5 dB Full Scale 48 kHz 20 Hz to 20 kHz 20 Bits 100 pF 47 k 2.4 V 0.8 V
Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
ANALOG PERFORMANCE
Min Resolution Signal-to-Noise Ratio (20 Hz to 20 kHz) No Filter (AD1854JRS) No Filter (AD1854KRS) With A-Weighted Filter (AD1854JRS) With A-Weighted Filter (AD1854KRS) Dynamic Range (20 Hz to 20 kHz, -60 dB Input) No Filter (AD1854JRS) No Filter (AD1854KRS) With A-Weighted Filter (AD1854JRS) With A-Weighted Filter (AD1854KRS) Total Harmonic Distortion + Noise (AD1854JRS) VO = 0 dB Total Harmonic Distortion + Noise (AD1854KRS) VO = 0 dB Total Harmonic Distortion + Noise (AD1854JRS and AD1854KRS) VO = -20 dB Total Harmonic Distortion + Noise (AD1854JRS and AD1854KRS) VO = -60 dB Analog Outputs Differential Output Range ( Full Scale) Output Impedance at Each Output Pin Output Capacitance at Each Output Pin Out-of-Band Energy (0.5 x FS to 100 kHz) CMOUT DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift Interchannel Crosstalk (EIAJ Method) Interchannel Phase Deviation Mute Attenuation De-Emphasis Gain Error
DIGITAL I/O (0 C to 70 C)
Typ 20 105 110 108 112 105 110 108 113 -97 -101 -89 -49
Max
Unit Bits dB dB dB dB dB dB dB dB dB dB dB dB
106 108 -88 -94
5.6 <200 20 -72.5 2.25 -11.0 -0.15 3.0 200 -120 0.1 -100 +11.0 +0.15 300
V p-p pF dB V % dB ppm/C dB Degrees dB dB
0.1
Min Input Voltage HI (VIH) Input Voltage LO (VIL) High Level Output Voltage (VOH) IOH = 1 mA Low Level Output Voltage (VOL) IOL = 1 mA Input Leakage (IIH @ VIH = 2.4 V) Input Leakage (IIL @ VIL = 0.8 V) Input Capacitance 2.2
Typ
Max 0.8
Unit V V V V A A pF
2.0 0.4 10 10 20
-2-
REV. A
AD1854
POWER
Min Supplies Voltage, Analog and Digital Analog Current Analog Current--Power-Down Digital Current Digital Current--Power-Down Dissipation Operation--Both Supplies Operation--Analog Supply Operation--Digital Supply Power-Down--Both Supplies Power Supply Rejection Ratio 1 kHz 300 mV p-p Signal at Analog Supply Pins 20 kHz 300 mV p-p Signal at Analog Supply Pins
TEMPERATURE RANGE
Typ 5 30 29 17 2.5 250 150 100
Max 5.5 35 33.5 20 5.5
Unit V mA mA mA mA mW mW mW mW dB dB
4.5 26 26 14 1.5
190 -60 -50
Min Specifications Guaranteed Functionality Guaranteed Storage 0 -55
Typ 25
Max 70 +125
Unit C C C
DIGITAL TIMING (Guaranteed over 0 C to 70 C, AVDD = DVDD = 5.0 V
10%)
Min tDMP tDMP tDMP tDML tDMH tDBH tDBL tDBP tDLS tDLH tDDS tDDH tPDRP MCLK Period (512 FS Mode) MCLK Period (384 FS Mode) MCLK Period (256 FS Mode) MCLK LO Pulsewidth (All Mode) MCLK HI Pulsewidth (All Mode) BCLK HI Pulsewidth BCLK LO Pulsewidth BCLK Period L/RCLK Setup L/RCLK Hold (DSP Serial Port Mode Only) SDATA Setup SDATA Hold PD/RST LO Pulsewidth 35 48 70 0.4 x tDMP 0.4 x tDMP 20 20 140 20 5 5 10 4 MCLK Periods
Max
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
DIGITAL FILTER CHARACTERISTICS
Min Passband Ripple Stopband Attenuation Passband Stopband Group Delay Group Delay Variation
Specifications subject to change without notice.
Typ 0.04 47 0.448 0.552 106/FS 0
Max
Unit dB dB FS FS sec s
REV. A
-3-
AD1854
ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION
Min DVDD to DGND AVDD to AGND Digital Inputs Analog Outputs AGND to DGND Reference Voltage Soldering -0.3 -0.3 DGND - 0.3 AGND - 0.3 -0.3
Max +6 +6 DVDD + 0.3 AVDD + 0.3 +0.3 (AVDD + 0.3)/2 300 10
Unit V V V V V C sec
DGND 1 MCLK 2 CLATCH 3 CCLK 4 CDATA 5 384/256 6 X2MCLK 7
28 27 26 25 24
DVDD SDATA BCLK L/RCLK PD/RST MUTE
AD1854
23 22
ZEROL TOP VIEW ZEROR 8 (Not to Scale) 21 IDPM0
20 19 18 17 16 15
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DEEMP 9 96/48 10 AGND 11 OUTR+ 12 OUTR- 13 FILTR 14
IDPM1 FILTB AVDD OUTL+ OUTL- AGND
PACKAGE CHARACTERISTICS
Min JA (Thermal Resistance [Junction-to-Ambient]) JC (Thermal Resistance [Junction-to-Case])
Typ 109 39
Max
Unit C/W C/W
ORDERING GUIDE
Model AD1854JRS AD1854JRSRL AD1854KRS AD1854KRSRL
Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
Package Description 28-Lead Shrink Small Outline 28-Lead Shrink Small Outline 28-Lead Shrink Small Outline 28-Lead Shrink Small Outline
Package Option RS-28 RS-28 on 13" Reels RS-28 RS-28 on 13" Reels
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1854 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. A
AD1854
PIN FUNCTION DESCRIPTIONS
Pin 1 2 3 4 5 6
Input/Output I I I I I I
Pin Name DGND MCLK CLATCH CCLK CDATA 384/256
Description Digital Ground. Master Clock Input. Connect to an external clock source at either 256, 384 or 512 FS. Latch input for control data. This input is rising-edge sensitive. Control clock input for control data. Control input data must be valid on the rising edge of CCLK. CCLK may be continuous or gated. Serial control input, MSB first, containing 16 bits of unsigned data per channel. Used for specifying channel-specific attenuation and mute. Selects the master clock mode as either 384 times the intended sample frequency (HI) or 256 times the intended sample frequency (LO). The state of this input should be hardwired to logic HI or logic LO, or may be changed while the AD1854 is in power-down/reset. It must not be changed while the AD1854 is operational. Selects internal clock doubler (LO) or internal clock = MCLK (HI). Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal input for more than 1024 LR Clock Cycles. De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used to impose a 50 s/15 s response characteristic on the output audio spectrum at an assumed 44.1 kHz sample rate. Selects 48 kHz (LO) or 96 kHz Sample Frequency Control. Analog Ground. Right Channel Positive line level analog output. Right Channel Negative line level analog output. Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference with parallel 10 F and 0.1 F capacitors to the AGND. Left Channel Negative line level analog output. Left Channel Positive line level analog output. Analog Power Supply. Connect to analog 5 V supply. Filter Capacitor connection, connect 10 F capacitor to AGND. Input serial data port mode control one. With IDPM0, defines one of four serial modes. Input serial data port mode control zero. With IDPM1, defines one of four serial modes. Left Channel Zero Flag Output. This pin goes HI when Left Channel has no signal input for more than 1024 LR Clock Cycles. Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation. Power-Down/Reset. The AD1854 is placed in a low power consumption mode when this pin is held LO. The AD1854 is reset on the rising edge of this signal. The serial control port registers are reset to the default values. Connect HI for normal operation. Left/Right clock input for input data. Must run continuously. Bit clock input for input data. Need not run continuously; may be gated or used in a burst fashion. Serial input, MSB first, containing two channels of 16, 18, 20, and 24 bits of twos complement data per channel. Digital Power Supply Connect to digital 5 V supply.
7 8 9
I O I
X2MCLK ZEROR DEEMP
10 11, 15 12 13 14 16 17 18 19 20 21 22 23 24
I I O O O O O I O I I O I I
96/48 AGND OUTR+ OUTR- FILTR OUTL- OUTL+ AVDD FILTB IDPM1 IDPM0 ZEROL MUTE PD/RST
25 26 27 28
I I I I
L/RCLK BCLK SDATA DVDD
REV. A
-5-
AD1854
OPERATING FEATURES Serial Data Input Port
The AD1854's flexible serial data input port accepts data in twos-complement, MSB-first format. The left channel data field always precedes the right channel data field. The input data consists of either 16, 18, 20, or 24 bits, as established by the mode select pins (IDPM0 Pin 21 and IDPM1 Pin 20) or the mode select bits (Bits 15 and 14) in the control register through the SPI (Serial Peripheral Interface) control port. Neither the pins nor the SPI controls has preference; to ensure proper control, the selection not being used should be tied LO. Therefore, when the SPI bits are used to control Serial Data Input Format, Pins 20 and 21 should be tied LO. Similarly, when the pins are to be used to select the Data Format, the SPI bits should be set to zeros. When the SPI Control Port is not being used, the SPI Pins (3, 4, and 5) should be tied LO.
Serial Data Input Mode
Figure 1 shows the right-justified mode (16-bit mode). L/RCLK is HI for the left channel, LO for the right channel. Data is valid on the rising edge of BCLK. The MSB is delayed 16-bit clock periods from an L/RCLK transition, so that when there are 64 BCLK periods per L/RCLK period, the LSB of the data will be right justified to the next L/RCLK transition. The right-justified mode can also be used with 20-bit or 24-bit inputs as selected in Table I. Figure 2 shows the I2S-justified mode. L/RCLK is LO for the left channel and HI for the right channel. Data is valid on the rising edge of BCLK. The MSB is left justified to an L/RCLK transition but with a single BCLK period delay. The I2S-justified mode can be used with 16-/18-/20- or 24-bit inputs. Figure 3 shows the left-justified mode. Note: Left-justified mode is selected by pulsing IDPM1 (Pin 20) with bit clock, that is, tying bit clock to IDPM1 while IDPM0 (Pin 21) is tied LO. Leftjustified can only be selected this way, it cannot be selected through SPI Control Port. L/RCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. The MSB is leftjustified to an L/RCLK transition, with no MSB delay. The left-justified mode can be used with 16-/18-/20- or 24-bit inputs. Note that the AD1854 is capable of a 32 x FS BCLK frequency "packed mode" where the MSB is left-justified to an L/RCLK transition, and the LSB is right-justified to an L/RCLK transition. L/RCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. Packed mode can be used when the AD1854 is programmed in rightjustified mode. Packed mode is shown is Figure 4.
The AD1854 uses two multiplexed input pins to control the mode configuration of the input data port mode as follows:
Table I. Serial Data Input Modes
IDPM1 (Pin 20) 0 0 1 1 Bit Clock
IDPM0 (Pin 21) 0 1 0 1 0
Serial Data Input Format Right Justified (16 Bits) I2S-Compatible Right Justified (20 Bits) Right Justified (24 Bits) Left Justified
Table II. Frequency Mode Settings
FS Normal, 32 kHz-48 kHz Normal, 32 kHz-48 kHz Normal, 32 kHz-48 kHz Normal, 32 kHz-48 kHz Double FS (96 kHz) Double FS (96 kHz) Double FS (96 kHz) Double FS (96 kHz)
96/48 0 0 0 0 1 1 1 1
MCLK 256 x FS 384 x FS 512 x FS 128 x FS (384/2) x FS 256 x FS
X2MCLK 0 0 1 1 0 0 1 1
384/256 0 1 0 1 0 1 0 1
Note
Not Allowed
Not Allowed
L/RCLK INPUT BCLK INPUT SDATA INPUT
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
MSB-1 MSB-2
LSB+2 LSB+1
LSB
MSB
MSB-1 MSB-2
LSB+2 LSB+1
LSB
Figure 1. Right-Justified Mode
L/RCLK INPUT BCLK INPUT SDATA INPUT LEFT CHANNEL RIGHT CHANNEL
MSB
MSB-1 MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1 MSB-2
LSB+2 LSB+1
LSB
MSB
Figure 2. I2S-Justified Mode
-6-
REV. A
AD1854
L/RCLK INPUT LEFT CHANNEL RIGHT CHANNEL
BCLK INPUT SDATA INPUT
MSB
MSB-1 MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1 MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
Figure 3. Left-Justified Mode
L/RCLK INPUT LEFT CHANNEL RIGHT CHANNEL
BCLK INPUT SDATA INPUT
LSB
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
Figure 4. 32 x FS Packed Mode
t CCP
CDATA D15
t CHD
D14 D0
CCLK
t CCH t CCL t CSU t CLL t CLH
CLATCH
Figure 5. Serial Control Port Timing
Serial Control Port
The AD1854 serial control port is SPI-compatible. SPI (Serial Peripheral Interface) is an industry standard serial port protocol. The write-only serial control port gives the user access to: select input mode, soft power-down control, soft de-emphasis, channelspecific attenuation and mute (both channels at once). The AD1854 serial control port consists of three signals, control clock CCLK (Pin 4), control data CDATA (Pin 5), and control latch CLATCH (Pin 3). The control data input must be valid on the control clock rising edge, and the control clock must make a LO to HI transition when there is valid data. The control latch must make a LO-to-HI transition after the LSB has been clocked into the AD1854, while the control clock is inactive. The timing relation between these signals is shown in Figure 5. The control bits are assigned as in Table IV.
Table III. Digital Timing
The serial control port is byte oriented. The data is MSB first, and is unsigned. There is one control register for the left channel or the right channel, as distinguished by Bit Data 10. For power-up and reset, the default settings are: Data 11 the mute control bit, reset default state is LO, which is the normal (nonmuted) setting. Data 10 is LO, the Volume 9 through Volume 0 control bits have a reset default value of 11 1111 1111, which is an attenuation of 0.0 dB (i.e., full scale, no attenuation). The intent with these reset defaults is to enable AD1854 applications without requiring the use of the serial control port. For those users who do not use the serial control port, it is still possible to mute the AD1854 output by using the MUTE (Pin 23) signal. Note that the serial control port timing is asynchronous to the serial data port timing. Changes made to the attenuator level will be updated on the next edge of the L/RCLK after the CLATCH write pulse as shown in Figure 8. The SPI port can be used in either of two modes, Burst Mode, or Continuous CCLK Mode, as described below.
Continuous CCLK Mode
Min tCCH tCCL tCCP tCSU tCHD tCLL tCLH CCLK HI Pulsewidth CCLK LO Pulsewidth CCLK Period CDATA Setup Time CDATA Hold Time CLATCH LO Pulsewidth CLATCH HI Pulsewidth 40 (Burst Mode) 40 (Burst Mode) 80 (Burst Mode) 10 10 10 130 (Burst Mode)
Unit ns ns ns ns ns ns ns
In this mode, the maximum CCLK frequency is 3 MHz. The CCLK can run continuously between transactions. Please note that the LO-to-HI transition of the CLATCH with respect to the rising edge of CCLK must be at least 130 ns, as shown in Figure 6.
Table IV. Serial Control Bit Definitions
MSB Data 15 Data 14 Data 13 Data 12 IDPM1 Input Mode1 Select IDPM0 Input Mode0 Select Soft PowerDown LSB Data 0
Data 11
Data 10 Data 9
Data 8
Data 7
Data 6 Volume Control Data
Data 5 Volume Control Data
Data 4 Volume Control Data
Data 3 Volume Control Data
Data 2 Volume Control Data
Data 1
Soft 1/Mute 1/Right De0/Normal 0/Left Emphasis (Nonmute)
Volume Volume Volume Control Control Control Data Data Data
Volume Volume Control Control Data Data
REV. A
-7-
AD1854
CLATCH >130ns CCLK
CDATA
20
40
60
80
100 TIME - ns
120
140
160
180
Figure 6. SPI Port Continuous CCLK Mode
CLATCH
CCLK
CDATA
200
400
600
800
1000 TIME - ns
1200
1400
1600
1800
Figure 7. SPI Port Burst Mode
Burst Mode Output Drive, Buffering and Loading
To operate with SPI CCLK frequencies up to 12.288 MHz, the SPI port can be operated in Burst Mode. This means that when CLATCH is high, CCLK cannot be HI, as shown in Figure 7.
Mute
The AD1854 analog output stage is able to drive a 1 k (in series with 2 nF) load.
Power-Down Reset
The AD1854 offers two methods of muting the analog output. By asserting the MUTE (Pin 23) signal HI, both the left and right channel are muted. As an alternative, the user can assert the mute bit in the serial control register (Data 11) HI. The AD1854 has been designed to minimize pops and clicks when muting and unmuting the device.
Smooth Volume Control with Auto Ramp Up/Down
The AD1854 incorporates ADI's 1024 step "Smooth Volume Control" with auto ramp up/down. Once per L/RCLK cycle, the AD1854 compares current volume level register to the volume level request register Data 9:0. If different, volume is adjusted one step/sample. Therefore, a change from max to min volume takes 1024 samples or about 20 ms as shown in Figure 8.
The AD1854 offers two methods for power-down and reset. When the PD/RST input (Pin 24) is asserted LO, the AD1854 is reset. As an alternative, the user can assert the soft powerdown bit (Data 13) HI. All the registers in the AD1854 digital engine (serial data port, interpolation filter and modulator) are zeroed. The two 8-bit registers in the serial control port are initialized back to their default values. The user should wait 100 ms after bringing PD/RST HI before using the serial data input port and the serial control input. The AD1854 is designed to minimize pops and clicks when entering and exiting the powerdown state.
De-Emphasis
0 VOLUME REQUEST REGISTER
LEVEL - dB
The AD1854 offers digital de-emphasis, supporting 50 s/15 s digital de-emphasis intended for "Redbook" 44.1 kHz sample frequency playback from Compact Discs. The AD1854 offers control of de-emphasis by asserting the DEEMP input (Pin 9) HI or by asserting the de-emphasis register bit (Data 12) HI. The AD1854's de-emphasis is optimized for 44.1 kHz but will scale to the other sample frequencies.
Control Signals
-60
0 ACTUAL VOLUME REGISTER
-60 TIME
The IDPM0, IDPM1, and DEEMP control inputs are normally connected HI or LO to establish the operating state of the AD1854. They can be changed dynamically (and asynchronously to L/RCLK and the master clock) as long as they are stable before the first serial data input bit (i.e., MSB) is presented to the AD1854.
20ms
Figure 8. Smooth Volume Control
-8-
REV. A
AD1854
Timing Diagrams
The serial data port timing is shown in Figures 9 and 10. The minimum bit clock HI pulsewidth is tDBH and the minimum bit clock LO pulsewidth is tDBL. The minimum bit clock period is tDBP. The left/right clock minimum setup time is tDLS and the left/right clock minimum hold time is tDLH. The serial data
tDBH
BCLK
minimum setup time is tDDS and the minimum serial data hold time is tDDH. The power-down/reset timing is shown in Figure 11. The minimum reset LO pulse width is tPDRP (four MCLK periods) to accomplish a successful AD1854 reset operation.
tDBP
tDBL tDLS
L/RCLK
SDATA LEFT-JUSTIFIED MODE
tDDS
MSB MSB-1
tDDH
SDATA I2S-JUSTIFIED MODE
tDDS
MSB
tDDH
SDATA RIGHT-JUSTIFIED MODE
tDDS
MSB
tDDS
LSB
tDDH
tDDH
Figure 9. Serial Data Port Timing
tDBH
BCLK
tDBP
tDLS
L/RCLK
tDBL
tDLH tDDS
MSB MSB-1
SDATA LEFT-JUSTIFIED DSP SERIAL PORT STYLE MODE
tDDH
Figure 10. Serial Data Port Timing-DSP Serial Port Style Mode
tDMP
MCLK
tDMH
PD/RST
tDML tPDRP
Figure 11. Power-Down/Reset Timing
REV. A
-9-
AD1854
MCLK/SR SELECT SELECT RATE X2MCLK 384/256 96/48 DVDD SPDIF DIRECT DIRECT 44.1 48.0 96.0 0 0 0 0 0 0 0 0 1 MCLK 11.2896 12.2880 12.2880
MCLK/SR SEL JP1
R3 10k
R2 10k
R1 10k
AD1854 STEREO DAC
DVDD C3 100nF AVDD C2 100nF
SDATA AUDIO DATA LRCLK SCLK MCLK
OUTPUT BUFFERS AND LP FILTERS
DVDD 96/48 AVDD OUTL- C14 1nF, NP0 C13 1nF, NP0 R16 1.96k R9 2.15k R8 953 C9 390pF NP0 R20 549 J1 LEFT OUT
I/F MODE RJ, 16-BIT I2S RJ, 20-BIT RJ, 24-BIT LJ
IDPM1 IDPM0 0 0 1 1 BCLK DVDD 0 1 0 1 0
384/256 X2MCLK SDATA OUTL+ L/RCLK BCLK R17 1.96k
U3B
R10 953 C10 390pF NP0
1 53.6k
SSM2135
C15 2.2nF NP0
I/F MODE
JP2
R11 2.15k
R4 10k
R5 10k
U1 AD1854JRS MCLK
IDPM0 IDPM1 R18 1.96k OUTR- C17 1nF, NP0 C16 R19 1nF, NP0 1.96k OUTR+ R15 2.15k R13 2.15k R12 953
3RD ORDER LP BESSEL FILTER CORNER FREQUENCY: 92kHz GROUP DELAY: ~2.8 s
DE-EMPHASIS MUTE
DEEMP MUTE CLATCH CCLK CCLK CDATA CDATA ZR ZEROR ZL ZEROL CLATCH
+AVCC C11 390pF NP0 C5 100nF R21 549 J2 RIGHT OUT
U3A
R14 953 C12 390pF NP0 C18 2.2nF SSM2135 NP0 C6 100nF 53.6k
1
RST
FILTR FITLB AGND AGND C1 100nF + C8 - 10 F + C7 - 10 F
-AVEE
PD/RST DGND
DGND CDATA CONTROL PORT CCLK CLATCH C4 100nF NOTE: = DGND = AGND ZR 3 ZL U2A HC04 1 2 U2B HC04 4 R6 221 DVDD CR1 ZERO LEFT FB1 600Z
CR2 ZERO RIGHT R7 221
Figure 12. Evaluation Board Circuit
-10-
REV. A
AD1854
TYPICAL PERFORMANCE
Figures 13 through 20 illustrate the typical analog performance of the AD1854 as measured by an Audio Precision System Two. Signal-to-Noise and THD+N performance are shown under a range of conditions. Figure 14 shows the power supply rejection
-60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 -155 -160 0 2 4 6 8 10 12 14 FREQUENCY - kHz 16 18 -60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 -155 -160 20
performance of the AD1854. Figure 15 shows the noise floor of the AD1854. The digital filter transfer function is shown in Figure 16. The two-tone test in Figure 17 is per the SMPTE Standard for Measuring Intermodulation Distortion.
0
0
-20
-20
-40 dBr - A
-40 dBr - B
dBr - B
dBr - A
dBr - B
-60
-60
-80
-80
-100
-100
-120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 AMPLITUDE - dBFS
-120 0
Figure 13. THD+N at 1 kHz, -0.5 dBFS (8K-Point FFT)
Figure 16. THD+N vs. Level at 1 kHz
-40 -45 -50 -55 -60 -65
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -105 0 2 4 6 10 12 14 8 FREQUENCY - kHz 16 18 -110 20
-40 -45 -50 -55
dBr - B
-40 -45 -50 -55 -60 -65 -70 -75 -80 -85 50 100 200 2k 500 1k FREQUENCY - Hz 5k 10k 20k -90
dBr - B
dBr - A
-75 -80 -85 -90 -95
dBr - A
-70
-60 -65 -70 -75 -80 -85 -90 20
-100 -105 -110
Figure 14. THD+N vs. Frequency at -0.5 dBFS
Figure 17. Power Supply Rejection to 300 mV p-p on AVDD
0 -10 -20 -30 -40 -50 -60 dBr - A -70 -80 -90
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 dBr - B
dBr - A
0 -10 -20 -30 -40 -50 -60 -70 -80 -90
0 -10 -20 -30 -40 -50 -60 -70
-100 -110 -120 -130 -140 -150 -160
-100 -110 -120 -130 -140 -150 -160
-80 -90 -100 -110 -120 -130 -140 -150 0 2 4 6 8 10 12 14 FREQUENCY - kHz 16 18 -160 20
0
2
4
6
8 10 12 14 FREQUENCY - kHz
16
18
20
Figure 15. Dynamic Range: 1 kHz at -60 dBFS (8K Point FFT) REV. A
Figure 18. Noise Floor, A-Weighted (8K-Point FFT)
-11-
AD1854
0 -10 MAGNITUDE RESPONSE - dB -20 -30 -40 0 -10 -20 -30 -40 -50 -60 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 2 4 6 8 10 12 14 FREQUENCY - kHz 16 18 -150 20
-50 -60 -70 -80 -90 -100 0 20 40 60 80 100 FREQUENCY - kHz 120 140 160
-70 -80 -90
-100 -110 -120 -130 -140 -150
Figure 19. Digital Filter Response
Figure 20. Two-Tone Test
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Shrink Small Outline Package (SSOP) (RS-28)
0.407 (10.34) 0.397 (10.08)
28
15
0.32 (8.20) 0.29 (7.40)
1 14
0.22 (5.60) 0.20 (5.00)
0.079 (2.0) MAX
PIN 1
0.073 (1.85) 0.065 (1.65)
-12-
REV. A
PRINTED IN U.S.A.
0.002 (0.05) MIN
0.026 (0.65) BSC
0.015 (0.38) SEATING 0.009 (0.22) PLANE
0.01 (0.25) 0.004 (0.09)
8 0
0.037 (0.95) 0.022 (0.55)
C3694-2.5-4/00 (rev. A)
dBr - A
dBr - B

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